MICRO CONTROLLER 8051

MICRO CONTROLLER
INTRODUCTION

The 89c51RD2xx is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Philips high-density nonvolatile memory technology and is compatible with industry-standard MCS-51 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the P89C51RD2xx is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.

Features
 Compatible with MCS-51 Products
 4K Bytes of In-System Reprogrammable Flash Memory – Endurance: 1000 Write/Erase Cycles.
 Fully Static Operation: 0Hz to 24MHz
 Three-level Program Memory Lock
 128 x 8- bit Internal RAM
 32 Programmable I/O Lines
 Two 16-bit Timer/Counters
 Six Interrupt Sources
 Programmable Serial Channel
 Low-power Idle and Power-down Modes




Figure.1 Block Diagram of the AT89C core
















For more information on the individual devices and features, refer to the Hardware Descriptions and Data Sheets of the specific device.









Fig.1 Oscillator Connection.

The P89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the P89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.


Fig.2 External Clock Drive Configuration















Fig.3 Memory Structure of the 8051.
Memory Organization
Program Memory
Figure 4 shows a map of the lower part of the program memory. After reset, the CPU begins execution from location 0000H. As shown in fig.4, each interrupt is assigned a fixed location in program memory. The interrupt causes the CPU to jump to that location, where it executes the service routine. External Interrupt 0, for example, is assigned to location 0003H. If External Interrupt 0 is used, its service routine must begin at location 0003H. If the interrupt is not used, its service location is available as general purpose.

Fig. 4 Program Memory.

Program memory addresses are always 16 bits wide, even though the actual amount o program memory used may be less than 64Kbytes. External program execution sacrifices two of the 8-bit ports, P0 and P2, to the function of addressing the program memory.

Data Memory

The right half of Figure 3 shows the internal and external data memory spaces available on Philips Flash microcontrollers. Fig.6 shows a hardware configuration for accessing up to 2K bytes of external RAM. In this case, the CPU executes from internal flash. Port0 serves as a multiplexed address/data bus to the RAM, and 3 lines of Port 2 are used to page the RAM. The CPU generates RD and WR signals as needed during external RAM accesses. You can assign up to 64K bytes of external data memory. External data memory addresses can be either 1 or 2bytes wide. One-byte addresses are often used in conjunction with one or more other I/O lines to page the RAM, as shown in Fig.6. Two-byte addresses can also be used, in which case the high address byte is emitted at Port2.


Internal data memory addresses are always 1 byte wide, which implies an address space of only 256bytes. However, the addressing modes for internal RAM can infact accommodate 384 bytes. Direct addresses higher than 7FH access one memory space and indirect addresses higher than 7FH access a different memory space. Thus, Figure.7 shows the Upper 128 and SFR space occupying the same block of addresses, 80H through FFH, although they are physically separate entities. Figure.8 shows how the lower 128 bytes of RAM are mapped. The lowest 32 bytes are grouped into 4 banks of 8 registers. Program instructions call out these registers as R0 through R7. Two bits in the Program Status Word (PSW) select which register bank is in use. This architecture allows more efficient use of code space, since register instructions are shorter than instructions that use direct addressing.






Fig.6 The lower 128 bytes of Internal RAM

The next 16 bytes above the register banks form a block of bit-addressable memory space. The microcontroller instruction set includes a wide selection of single-bit instructions, and these instructions can directly address the 128 bits in this area. These bit addresses are 00H through 7FH. All of the bytes in the Lower 128 can be accessed by either direct or indirect addressing.











Special Function Register Map
8 Bytes
F8 FF
F0 B F7
E8 EF
E0 ACC E7
D8 DF
D0 PSW(1) D7
C8 T2C0N(1)(2) T2MOD(2) RCAP2L(2) RCAP2H(2) TL2(2) TH2(2) CF
C0 C7
B8 IP(1) BF
B0 P3 B7
A8 IE(1) AF
A0 P2 A7
98 SCON(1) SBUF 9F
90 PI 97
88 TCON(1) TMOD(1) TLO TLI THO TH1 BF
80 PO SP DPL DPH PCON(1) 87
Bit Addressable
Notes: 1. SFRs converting mode or control bits
2. AT89C52only

Power-on Reset

The reset input is the RST pin, which is the input to a Schmitt Trigger. A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. The CPU responds by generating an internal reset.
The external reset signal is asynchronous to the internal clock. The RST pin is sampled during State 5 Phase 2 of every machine cycle. The port pins will maintain their current activities for 19 oscillator periods after a logic 1 has been sampled at the RST pin; that is, for 19 to 31 oscillator periods after the external reset signal has been applied to the RST pin.
The internal reset algorithm writes 0s to all the SFRs except the port latches, the Stack Pointer and SBUF. The port latches are initialized to FFH, the Stack Pointer to 07H, and SBUF is indeterminate. The internal RAM is not affected by reset. On power up the RAM content is indeterminate.
REGISTER REST VALUE
-------------------------------------------------------------------------
PC 0000H
ACC 00H
B 00H
PSW 00H
SP 07H
DPTR 0000H
P0-P3 FFH
IP XXX0000B
IE 0XX0000B
TMOD 00H
TCON 00H
TH0 00H
TL0 00H
TH1 00H
SCON 00H
SBUF Indeterminate
PCON (NMOS) 0XXXXXXXB
PCON (CMOS) 0XXX0000B

Interrupts

The P89C51 provides 5 interrupt sources. The External Interrupts INT0 and INT1 can each be either level-activated or transition-activated, depending on bits IT0 and IT1 in Register TCON. The flags that actually generate these interrupts are bits IE0 and IE1 in TCON. When an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. If the interrupt was level-activated, then the external requesting source is what controls the request flag, rather than the on-chip hardware.

The Timer0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in their respective Timer/Counter registers (except see Timer0 in Mode3). When a timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to.
The Serial Port Interrupt is generated by the logical OR of RI and TI. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine will normally have to determine whether it was RI or TI that generated the interrupt, and the bit will have to be cleared in software.
All of the bits that generate interrupts can be set or cleared by software, with the same result as thought it had been set or cleared by hardware. This is, interrupts can be generated or pending interrupts can be canceled in software.
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once.
The interrupt flags are sampled a S5P2 of every machine cycle. The samples are polled during the following machine cycle. If one of the flags was in a set condition at S5P2 of the preceding cycle, the polling cycle will find it and the interrupt system will generate an LCALL to the appropriate service routine, provided this hardware-generated LCALL is not blocked by any of the following conditions:
1. An interrupt of equal or higher priority level is already in progress.
2. The current (polling) cycle is not the final cycle in the execution of the instruction in progress.
3. The instruction in progress is RET1 or any write to the IE or IP registers.
Any of these three conditions will block the generation of the LCALL to the interrupt service routine. Condition 2 ensures that instruction in progress will be completed before vectoring to any service routine. Condition 3 ensures that if the instruction in progress is RET1 or any access to IE or IP, then at least one more instruction will be executed before any interrupt is vectored to.
The poling cycle is repeated with each machine cycle, and the values polled are the values that were present at S5P2 of the previous machine cycle. Note that if any interrupt flag is active but not being responded for one of the above conditions, if the flag is not still active when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle is new.

The processor acknowledges an interrupt request by executing hardware generated LCALL to the appropriate servicing routine. In some cases it also clears the flag that generated the interrupt, and in other cases it doesn’t. It never clears the Serial Port flag. This has to be done in the user’s software. It clears an external interrupt flag (IE0 or IE1) only if it was transition-activated. The hardware generated LCALL pushes the contents of the Program Counter onto the Stack (but it does not save the PSW) and reloads the PC with an address that depends on the source of the interrupt being vectored to. Execution proceeds from that location until the RET1 instruction is encountered. The RET1 instruction informs the processor that this interrupt routine is no longer in progress, then pops the top two bytes from the stack and reloads the Program Counter. Exception of the interrupted program continues fro where it left off.

Note that a simple RET instruction would also have returned execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt was still in progress, making future interrupts impossible.

External Interrupts
The external sources can be programmed to be level-activated or transition-activated by setting or clearing bit IT1 or IT0 in Register TCON. If ITx=0, external interrupt x is triggered by a detected low at the INTX pin. If ITx=1, external pin x is edge triggered. In this mode if successive samples of the INTX pin show a high in one cycle and a low in the next cycle, interrupt request flag IEx in TCON is set. Flag bit IEx then request the interrupt.
Since the external interrupt pins are sampled once each machine cycle, an input high or low should hold for at least 12 oscillator periods to ensure sampling. If the external interrupt is transition-activated, the external source has to hold the request pin high for at least once cycle, and then hold it low for at least one cycle. This is done to ensure that transition is seen so that interrupt request flag IEx will be set. The CPU will automatically clear IEx when the service routine is called.

If the external interrupt is level-activated, the external source has to hold the request active until the requested interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated.
To use any of the interrupts in the 89C51 Family, the following three steps must be taken.
1. Set the EA (enable all) bit in the IE register to 1.
2. Set the corresponding individual interrupt enable bit in the IE register to 1.
3. Begin the interrupt service routine at the corresponding vector.
Address of that interrupt. See Table below.
Interrupt Source Vector Address
----------------------------------------------------------------
IE0 0003H
TF0 000BH
IE1 0013H
TF1 001BH
RI & TI 0023H
----------------------------------------------------------------
In addition, for external interrupts, pins INT0 and INT1(P3.2 and P3.3) must be set to 1, and depending on whether the interrupt is to be level or transition activated, bits IT0 or IT1 in the TCON register may need to be set to 1.
ITx=0 level activated
ITx=1 transition activated Priority within level is only to resolve simultaneous requests of the same priority level. Form high to low, interrupt sources are listed below:
IE0 highest priority
TF0
IE1
TF1R1 or T1 lowest priority


Timer Set-Up
The tables below give some values for TMOD which can be used to set up Timer 0 and Timer 1 in different modes. It is assumed that only one timer is being used at a time. If it is desired to run Timers 0 and 1 simultaneously, in any mode the value in the TMOD for timer 0 must be ORed with value shown for Timer 1. For example, if it is desired to run Timer 0 in mode 1 GATE (external control), and Timer 1 in mode 2 COUNTER, then value that must be loaded into TMOD is 69H (09H from the table for Timer0, ORed with 60H from the table for Timer 1).
Moreover, it is assumed that the user, at this point, is not ready to turn the timers on and will do that at a different point in the program by setting bit TRx (in TCON) to 1.

TIMER/COUNTER 0
As a Timer:
Mode Function TMOD (internal control) TMOD (external control)

0 13-bit Timer 00H 08H
1 16-bit Timer 01H 09H
2 8-bit Auto-Reload 02H 0AH
3 Two 8-bit Timers 03H 0BH


As a Counter:
Mode Function TMOD (internal control) TMOD (external control)

0 13-bit Counter 04H 0CH
1 16-bit Counter 05H 0DH
2 8-bit Auto-Reload 06H 0EH
3 One 8-bit Counter 07H 0FH




TIMER/COUNTER 1

As a Timer:
Mode Function TMOD (internal control) TMOD (external control)

0 13-bit Timer 00H 80H
1 16-bit Timer 10H 90H
2 8-bit Auto-Reload 20H A0H
3 Does not run 30H B0H



As a Counter
Mode Function TMOD (internal control) TMOD (external control)

0 13-bit Counter 40H C0H
1 16-bit Counter 50H D0H
2 8-bit Auto-Reload 60H A0H
3 Not available --- ---

Serial Port Set-Up


The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read form the register. (However, if the first byte still hasn’t been read by the time reception of the second byte is complete, one of the bytes will be lost.) The serial port receive and transmit registers are both accessed at Special Function Register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register.

The serial port can operate in 4 modes:

Mode 0: Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/received (LSB first). The baud rate is fixed at 1/12th oscillator frequency.

Mode 1: 10 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive; the stop bit goes into RB8 in Special Function Register SCON. The baud rate is variable.

Mode 2: 11 bits are transmitted (trough TxD) or received (through RxD): start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB is SCON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On receive; the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64th oscillator frequency.

Mode 3: 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, Mode 3 is the same as Mode2 in all aspects except baud rate. The baud rate in Mode 3 is variable.


Timer 1 Generated Commonly Used Baud Rages

The values for the different modes of operation of the serial port are shown in the table below:
MODESCON SM2 Variation

0 10H Single Processor
1 50H Environment
2 90H (SM2 = 0)
3 D0H

0 Not Available Multiprocessor
1 70H Environment
2 B0H (SM2 =1)
3 F0H -------------

GENERATING BADU RAGES
Serial Port in Mode 0:
Mode 0 has a fixed baud rate, which is 1/12th oscillator frequency. To run the serial port in this mode none of the Timer/Counters need to be set up. Only the SCON register needs to be defined.

Baud Rate = Oscillator Frequency /12
Serial Port in Mode 1:

Mode1 has a variable baud rate. The baud rate is generated by Timer 1.
For this purpose, Timer 1 is used in mode2 (Auto-Reload).

Baud Rate = (K x Osc.Freq) / (32 x 12 x [256 – (TH1)])
If SMOD =0, then K=1.
If SMOD =1, then K =2 (SMOD is in the PCON register).

Most of the time the user knows the baud rate and needs to know the reload value for TH1.

TH1 = 256 – (K x Osc.Freq) / (384 x baud rate)

TH1 must be an integer value. Rounding off TH1 to the nearest integer may not produce the desired baud rate. In this case, the user may have to choose another crystal frequency.
Since the PCON register is not bit addressable, one way to set the bit is logical ORing the PCON register (i.e. ORL PCON, #80H). The address of PCON is 87H. Serial Port in Mode2:
The baud rate is fixed in this mode and is 1/32 or 1/64 of the oscillator frequency, depending on the value of the SMOD bit in the PCON register.

In this mode none of the Timers are used and the clock comes form the internal phase 2 clock.
SMOD = 1, Baud Rate = 1/32 Osc.Freq.
SMOD =0, Baud Rate = 1/64 Osc.Freq.

Circuit of 8051.
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